Voltage reference circuits are important in a wide-variety of applications including analog-to-digital conversion, sensor circuits, signal processing circuits, to name a few. For example, an analog-to-digital converter (ADC) circuit is arranged to receive an analog input signal and convert it into a digital code by comparing (e.g., sometimes repeatedly comparing) the analog input signal to the reference voltage. Depending on the architecture of the ADC circuit, the accuracy in the resulting digital code may be largely dependent on the accuracy of the reference voltage.
ADCs may employ a wide variety of architectures, such as the integrating, successive approximation, flash, and the delta-sigma architectures. Recently, the pipelined analog-to-digital converter (ADC) has become a popular ADC architecture for use in high-speed applications such as CCD imaging, ultrasonic medical imaging, digital video, and communication technologies such as cable modems and fast Ethernet. Pipelined ADCs are typically chosen because of their high accuracy, high throughput rate, and low power consumption. Moreover, the pipeline architecture generally provides better performance for a given power and semiconductor die area than other ADC architectures.
An example of a conventional pipelined ADC (100) is shown in FIG. 1A. As shown in the figure, the conventional pipelined ADC (100) includes an array of N gain stages. Each of the gain stages is connected in series to the previous gain stage. Each gain stage is also connected to a decoder logic circuit (not shown).
Each pipeline gain stage has a multiplying digital-to-analog converter (MDAC) circuit that includes a sample-and-hold amplifier (SHA), a sub-ADC circuit (k-bit ADC), a digital-to-analog converter (k-bit DAC), a summer (+), and a gain stage (AV). The MDAC is arranged to receive an input signal (VINPUT) and store the input signal with the sample-and-hold amplifier (SHA). The sub-ADC generates a corresponding k-bit digital code for the stored input level and then the digital code is converted back to the analog domain through the digital-to-analog converter (DAC). The sampled input signal from the SHA is subtracted from the output of the DAC by the summer, and then multiplied by 2k via the gain stage (AV), where k is the resolution of MDAC.
The residue voltage (VRESIDUE) from the first gain stage (e.g., stage 1) becomes the analog input voltage to the next gain stage (e.g., stage 2) of the pipeline. That is, VINPUT(2)=VRESIDUE(1). The residue voltages (VRES(i)) continue through the various pipeline of gain stages (1−N), resulting in a series of digital coefficient (e.g., Di) from the output of each k-bit ADC from each MDAC.
FIG. 1B is a graph that illustrates an ideal residue voltage in a pipeline ADC system. In this figure, the input voltage (VINPUT) is provided along the x-axis and the resulting residue voltage (VRESIDUE) is provided along the y-axis. The output residue voltage (VRESIDUE) from each MDAC pipeline stage is generated by the following transfer function: VRESIDUE=VINPUT*2i−VREF*Di, where i is the stage number of the MDAC, Di is digital code output from the ith stage DAC from the sub-ADC, and VREF is the corresponding reference signal.
The internal reference voltage (VREF) for the sub-ADC is sometimes generated as a pair of reference voltages. For example, VREFP and VREFN are positive and negative reference voltages for the k-bit ADC, where 2*(VREFP−VREFN) is the peak-to-peak range of the ADC, as illustrated in FIG. 1B.